Serial Peripheral Interface (SPI)

First
Previous
Next
Last

Table of Contents
Home

Slide
46 of 50

The serial peripheral interface (SPI) is the full-duplex, synchronous data transfer mechanism upon which the simpler serial input/output port (SIOP) is based. Differences between the SIOP and the SPI are discussed below.

Master mode transfers at 1/2, 1/4, 1/16, or 1/32 of the internal MCU clock frequency are supported by the SPI. In slave mode, transfers are synchronized by the shift clock from the external master device and can occur at frequencies up to that of the internal MCU clock.

The SPI also supports four different transfer protocols. Each one is defined by a unique combination of the clock phase (CPHA) and clock polarity (CPOL) bits in the SPI control register (SPCR). Unless masked otherwise, the SIOP only supports the single CPOL = CPHA = 1 protocol.

For proper operation in multiple master systems, SPI mode fault logic should be enabled. This is done by making the SS (slave select) pin an input when a device becomes the bus master. Normal transfers will take place as long as SS remains at logic one. When logic zero appears on SS, the fault detection hardware on the current master will automatically disable the SPI subsystem, make all of its pins as inputs, and generate an SPI interrupt. This releases the bus for a new master. The SIOP has no such fault detection mechanism.